1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same. More particularly, the present invention relates to an MRAM including a unit cell formed of one transistor and two magnetic tunnel junctions (MTJs) and a method for fabricating the same.
2. Description of the Related Art
MRAM, which is one type of next-generation memory device, has properties of both DRAM and SRAM, and also has nonvolatile characteristics of flash memory.
MRAM typically includes a unit cell formed of one pass transistor 10 and one MTJ layer 20 as shown in FIG. 1, or includes two pass transistors, i.e., a first pass transistor 22 and a second pass transistor 24, and two MTJ layers, i.e., a first MTJ layer 22a and a second MTJ layer 24a, as shown in FIG. 2.
The MRAM of FIG. 1 further includes a reference cell array (not shown) corresponding to an intermediate value between logic “0” and logic “1,” while in the MRAM of FIG. 2, a cell formed of the second pass transistor 24 and the second MTJ layer 24a is used as a reference cell of a cell formed of the first pass transistor 22 and the first MTJ layer 22a. 
Thus, in the MRAM of FIG. 2, when data (e.g., “1”) is recorded in the cell formed of the first pass transistor 22 and the first MTJ layer 22a, opposite data (e.g., “0”) is simultaneously recorded in the cell formed of the second pass transistor 24 and the second MTJ layer 24a. 
In the MRAM of FIG. 2, since a unit cell includes a main cell, where data is stored, and a reference cell, where inverted data of the data stored in the main cell is stored, a sensing margin of the MRAM is twice as wide as that of the MRAM of FIG. 1. Accordingly, data can be read more exactly using the MRAM of FIG. 2 than the MRAM of FIG. 1. Also, as shown in FIG. 2, since the main cell and the reference cell form a pair, noise in the unit cell can be reduced.
However, as a unit cell of the MRAM of FIG. 2 occupies a wider area than a unit cell of the MRAM of FIG. 1, the MRAM of FIG. 2 has a lower integration density than the MRAM of FIG. 1. However, because the MRAM of FIG. 1 has a smaller sensing margin than the MRAM of FIG. 2, a magnetic resistance (MR) ratio of the MTJ layer 20 should be higher than that of the first and second MTJ layers 22a and 24a, and the MTJ layer 20 should be uniform to normally operate the MRAM.
In FIGS. 1 and 2, reference numerals BL, DL, WL, and /BL respectively denote a bit line, a data line used with the bit line BL for recording data, a word line, and a bit line where inverted data of the data applied to the bit line BL is applied. The data line DL of FIG. 1 is disposed below the MTJ layer 20, as illustrated in FIGS. 3 and 4.
FIG. 3 illustrates a typical method for reading data recorded in an MRAM formed of one pass transistor and one MTJ layer.
Referring to FIG. 3, a predetermined voltage is applied to the word line WL such that the pass transistor 10 is turned on. Then, a read current IR is applied through the pass transistor 10 to the MTJ layer 20. Here, the data recorded in the MTJ layer 20 is read using a measured voltage. In FIG. 3, reference numerals S and D denote a source and a drain of the pass transistor 10. A conductive plug 26 is coupled to the drain D of the pass transistor 10 and a pad conductive layer 28 is formed on the conductive plug 26.
The foregoing method of reading data is similar to a method of reading data recorded in a MRAM having a twin-cell structure as shown in FIG. 2.
That is, in the MRAM of FIG. 2, the same amount of current is applied to both the main cell and the reference cell, and then voltages of bit lines BL and /BL are compared, and a difference therebetween is read. During this operation, drain voltages of the first and second pass transistors 22 and 24 may be changed to offset each other.
Meanwhile, a typical method of recording data in a MRAM formed of one pass transistor and one MTJ layer is performed by shifting a magnetized state of the MTJ layer.
Specifically, referring to FIG. 4, a predetermined first write current Iw1 and a predetermined second write current Iw2 are applied to the bit line BL and the data line DL, respectively. Here, a magnetic field occurs due to the first and second write currents Iw1 and Iw2, and a magnetized state of the MTJ layer 20 is shifted due to the magnetic field such that the MTJ layer 20 has magnetic resistance corresponding to data “0” or “1.”
In the MRAM having a twin cell structure as shown in FIG. 2, data is recorded by applying predetermined write currents to the bit lines BL and /BL and the data line DL.
Specifically, a current in a direction opposite to a direction in which a current is applied to the bit line BL is applied to the bit line /BL in a state in which the first pass transistor 22 and the second pass transistor 24 are turned off. As a result, the first MTJ layer 22a and the second MTJ layer 24a are polarized in opposite directions to have different magnetic resistances. That is, predetermined data is recorded in the first MTJ layer 22a while inverted data of the predetermined data is recorded in the second MTJ layer 24a. 
As described above, although the MRAM of FIG. 1 enables high integration density, an MR ratio thereof should be higher due to a low sensing margin and the MTJ layer should be uniform. The MRAM of FIG. 2 enables a high-speed operation, a sufficient sensing margin, and reduced noise, but has the disadvantage of a relatively low integration density owing to an increased area of a unit cell.